Description
… FBGA components. The SPD is programmed to JEDEC standard latency DDR4-2666 timing of 19-19-19 at 1.2V. Each 260-pin SODIMM uses gold contact fingers.NOTE: Image for Illustration Purposes OnlyFeaturesPower Supply: VDD=1.2VVDDQ = 1.2VVPP – 2.5VVDDSPD=2.2V to 3.6VFunctionality and operations comply with the DDR4 SDRAM datasheet16 internal banksBank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are availableData transfer rates: PC4-2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600Bi-directional Differential Data Strobe8-bit pre-fetchBurst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)Supports ECC error correction and detectionOn-Die Termination (ODT)Temperature sensor with integrated SPDThis product is in compliance with the RoHS directivePer DRAM Addressability is supportedInternal Vref DQ level generation is availableWrite CRC is supported at all speed gradesCA parity (Command/Address Parity) mode is supportedRoHS CompliantExtra InfoMemory Size: 8192MBModule Size: 8192MBMemory Type: DDR4Memory Package: SO-DIMMPin Configuration: 260 pinsMain Colour: Green
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